Intern- Engineering (Design)

Location: AZ - Chandler, United States

Company

hirify.global is a global semiconductor company developing products for data centers, servers, storage systems, and other technology applications.

What you will do

• Write and maintain RTL for digital logic blocks using Verilog and SystemVerilog.
• Analyze simulation, synthesis, and timing results, identify issues, and collaborate with design and verification engineers on resolutions.
• Contribute to automated design flows and scripts for synthesis, lint, CDC, and timing.
• Help design, implement, and integrate AI-based tools and workflows to improve design productivity.
• Research AI technologies and methodologies applicable to ASIC and IP design.
• Participate in technical meetings and reviews.

Requirements

• Currently enrolled in an Electrical Engineering, Computer Engineering, or related postgraduate program.
• Senior-level undergraduate standing or active postgraduate study is preferred.
• Knowledge of digital design and computer architecture, including academic projects using Verilog or SystemVerilog.
• Programming and scripting skills with Python, TCL, or Perl.
• Strong analytical, problem-solving, debugging, communication, and documentation skills.
• Ability to work part-time, up to 25 hours per week, while completing a degree program.

Nice to have

• Exposure to artificial intelligence applications for design or process improvement.
• Expected graduation in Summer 2027.

Culture & Benefits

• Part-time internship with up to 25 hours per week.
• Hands-on work alongside experienced IP design engineers.
• Exposure to storage controller SOC products used by server, storage, and hyperscale data center customers.
• Professional development supported through leadership and employee development programs.
• No travel required.