Analog Modeling & Testing Engineer Intern (Analog IC)

TL;DR

Analog Modeling & Testing Engineer Intern (Analog IC): Supporting the development of analog IP products with an accent on IC design, layout, and silicon characterization. Focus on modeling analog circuits in System Verilog, verifying simulations against Spice, and developing testing flows using Python.

Location: Cordoba, Argentina

Company

hirify.global provides semiconductor solutions that serve as the essential building blocks of data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Support IC design through layout, silicon evaluation, and characterization.
• Model analog circuits using System Verilog (SV).
• Verify SV simulations against spice simulations.
• Test analog circuits using python scripts and firmware.
• Run co-simulations between digital and analog designs.
• Develop and enhance flows that facilitate robust analog IC design.

Requirements

• Must be in the last year of a 5/5.5 year Engineering course at UTN-FRC, UTN-VM, UNC, or IUA, or pursuing a Master/PhD in Electrical Engineering at any university in Argentina.
• Intuitive and analytical understanding of transistor-level and CMOS circuit design.
• Experience in Verilog and spice simulations.
• Ability to define and adhere to project schedules.
• Effective written and verbal communication skills.

Nice to have

• Ability to write behavioral models for both analog and digital circuits.

Culture & Benefits

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Access to advanced analog training and professional development resources.