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Mixed-Signal Design & Verification Engineer Lead (ASIC)

Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
lead
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Spain/Portugal
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR
Mixed-Signal Design & Verification Engineer Lead (ASIC): Leading the development of design and verification frameworks for complex digital and mixed-signal ICs with an accent on analog/mixed-signal design, behavioral modeling, and ASIC verification. Focus on supervising multiple projects, defining analog-digital interfaces, running complex simulations, and supporting post-silicon validation for power management and signal management products.

Location: Barcelona, Spain or Portugal

Company

hirify.global develops integrated power semiconductors and systems power delivery architectures for portable and non-portable markets.

What you will do

  • Lead, supervise, mentor, and train the Mixed-Signal Design team.
  • Supervise multiple projects, ensuring quality metrics, deliverables, and schedules are met.
  • Define and lead design and verification frameworks for complex digital and mixed-signal ICs.
  • Perform analog and mixed-signal design, verification, validation, simulation, and debugging.
  • Define analog-digital interfaces, develop behavioral models, and analyze architectural trade-offs.
  • Collaborate with analog, layout, digital design, verification, and physical design engineers, including support for post-silicon validation.

Requirements

  • BSEE with 12 years of ASIC mixed-signal design experience, or MSEE with 8 years of experience.
  • Strong background in transistor-level and analog/mixed-signal circuit design, device mismatches, noise, linearity, layout, and the ASIC fabrication process.
  • Experience with Spectre, HSPICE, Cadence ADE-L and ADE-XL, Monte Carlo and noise simulations, stability analysis, DRC, and LVS.
  • Experience with Verilog-AMS mixed-mode simulations and Verilog, SystemVerilog, and Verilog-A behavioral modeling.
  • Knowledge of DFT techniques including SCAN, LBIST, ABIST, and IDDQ, as well as STA and mixed-signal timing and I/O constraints.
  • Strong leadership, communication, independent working, and cross-functional collaboration skills.

Nice to have

  • Automotive and ASIL standards experience.
  • Knowledge of power management applications and interfaces such as I2C, I3C, SPI, USB, and PMBUS.
  • Experience with GitLab and Cliosoft SOS.
  • Valid disability certificate.

Culture & Benefits

  • Inclusive culture focused on diversity, equity, teamwork, fairness, and tolerance.
  • Opportunity to work on leading-edge semiconductor products and innovation.
  • Equal opportunity employment environment.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’