Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization

Location: San Jose, California, United States

Salary: $266.2K–$392.2K USD annually for the Bay Area California market

Company

hirify.global develops FPGA technologies and the Quartus FPGA Compiler for next-generation digital designs.

What you will do

• Define and drive the technical roadmap for Quartus timing analysis, timing modeling, and timing optimization.
• Design and implement advanced timing engines for FPGA compilation, placement, routing, and timing closure.
• Develop graph-based, path-based, multi-corner multi-mode, incremental, and variation-aware timing analysis capabilities.
• Improve timing accuracy, signoff correlation, quality of results, runtime, and scalability for large FPGA designs.
• Design scalable data structures and optimization algorithms using parallelization, multi-threading, and incremental processing.
• Provide technical mentorship and collaborate with architecture, synthesis, placement, routing, verification, and software engineering teams.

Requirements

• MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
• 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
• Deep expertise in static timing analysis, timing closure, timing modeling and correlation, physical design optimization, RTL-to-GDS or RTL-to-bitstream flows, and MCMM analysis.
• Strong understanding of placement and routing algorithms, clock analysis and optimization, path-based analysis, timing exceptions, and incremental timing architectures.
• Extensive C++ development experience with large-scale optimization systems and high-performance EDA engines.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience developing FPGA compilation tools or working with Quartus Compiler, Timing Analyzer, Fitter, or Routing technologies.
• Expertise in path-based timing optimization, CRPR, latch-based timing analysis, timing-driven placement and routing, or variation-aware analysis.
• Experience designing multi-threaded or distributed EDA infrastructure.
• Patents, publications, standards contributions, or major product innovations demonstrating technical leadership.

Culture & Benefits

• Regular, full-time employment with Shift 1 in the United States of America.
• Incentive opportunities based on individual and company performance.
• Technical leadership across multiple engineering organizations and influence over future FPGA compiler capabilities.