Senior Verification Engineer

Location: Hsinchu, Taiwan. The role requires proof of the right to work in Taiwan and authorization to access export-controlled technology, or the ability to obtain the necessary approvals.

Company

hirify.global develops high-performance RISC-V compute platforms for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer devices.

What you will do

• Define verification strategies and test plans for cache and memory-subsystem architecture.
• Develop and maintain SystemVerilog and UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Create directed and constrained-random tests for coherency, concurrency, ordering, backpressure, flow control, errors, and integration behavior.
• Analyze failures, isolate root causes, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification quality early in development.
• Analyze coverage, close coverage holes, and contribute reusable methodology, automation, and debugging improvements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 3+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in CPU, memory-system, or cache verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering.
• Experience creating test plans and testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and the ability to work effectively across design and verification teams.

Nice to have

• Direct experience verifying cache or memory-subsystem functionality in multicore systems.
• Experience with subsystem integration and protocol interactions across multiple interfaces or bridge paths.
• Python or similar scripting and automation experience.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debugging.

Culture & Benefits

• Full-time individual-contributor position within the horizontal cache verification area.
• Collaborative work with architecture, design, and verification teams.
• Equal-opportunity and inclusive work environment.
• Employment is contingent on successful background and reference checks and applicable export-control authorization.