Junior ASIC Design Engineer (AI Infrastructure)

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Own digital logic blocks from high-level definition through micro-architecture, RTL coding, debugging, and backend implementation support.
• Design high-performance hardware solutions for complex AI infrastructure connectivity challenges.
• Coordinate with Architecture, Verification, and Backend teams as the point of contact for assigned logic blocks.
• Use lint, CDC, synthesis, timing, power, and internal quality-assurance tools to improve design robustness and efficiency.
• Apply design techniques to meet power, performance, and area targets.
• Contribute to methodology improvements, tool automation, verification, validation, and AI-assisted engineering workflows.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 0–2 years of experience in logic design, including relevant internships, university labs, or academic projects.
• Foundational knowledge of Verilog and/or SystemVerilog.
• Strong understanding of digital design principles and RTL coding fundamentals.
• Strong communication skills and the ability to learn, adapt, and collaborate across teams.

Nice to have

• Master’s degree in Electrical Engineering or a related field.

Culture & Benefits

• Opportunity to help establish a strategic R&D center in Israel.
• Work on semiconductor chips supporting large-scale AI infrastructure.
• Collaborate with cross-functional engineering teams and contribute to a new local engineering organization.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.