Staff CPU Microarchitect, Vector and Matrix Compute (RISC-V)

TL;DR

Staff CPU Microarchitect, Vector and Matrix Compute (RISC-V): Designing next-generation RISC-V CPU vector, floating-point, and matrix execution units for HPC and AI workloads with an accent on scalable architecture, heterogeneous compute, and performance, power, and area optimization. Focus on defining microarchitecture, solving complex data-movement and memory-hierarchy challenges, and translating workload requirements into silicon-ready designs.

Location: Remote, based in North America. Access to U.S. export-controlled technology requires eligibility under applicable U.S. export laws and may depend on citizenship, permanent residency, or prior license approval.

Salary: $100,000–$500,000, including base and variable compensation targets.

Company

Tenstorrent develops high-performance RISC-V CPUs and AI platforms spanning hardware, software, compilers, networking, and semiconductor technologies.

What you will do

• Define CPU architecture and microarchitecture for vector, floating-point, and matrix compute extensions.
• Design execution units and subsystems for HPC, AI inference, and AI training workloads.
• Translate workload requirements into scalable architectures optimized for performance, power, and area.
• Specify memory hierarchy, data movement, cache coherency, and CPU–AI accelerator interactions.
• Lead cross-functional work with architects, software teams, silicon designers, and external IP partners from concept through implementation.

Requirements

• 5+ years of CPU design experience focused on high-performance computing and AI acceleration.
• Experience designing matrix floating-point hardware, AI accelerators, vector processors, tensor engines, or machine-learning workloads.
• Strong knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and heterogeneous compute systems.
• Experience defining architectural specifications and leading cross-functional engineering teams through silicon implementation.
• Experience with RTL development and cutting-edge AI workloads.
• Eligibility to access U.S. export-controlled technology is required.

Nice to have

• Experience with open RISC-V computing and large-scale datacenter systems.
• Experience co-designing CPUs, AI accelerators, and memory subsystems.

Culture & Benefits

• Collaborative environment focused on curiosity and solving difficult technical problems.
• Opportunity to work with CPU, AI, and system architects on future RISC-V computing infrastructure.
• Competitive compensation package and benefits.
• Equal opportunity employment.