Junior Design Verification Engineer (Semiconductors)

TL;DR

Junior Design Verification Engineer (SystemVerilog/UVM): Developing and executing comprehensive verification plans to validate complex digital circuits with an accent on UVM environments and functional coverage. Focus on building efficient test benches, debugging simulation results, and collaborating with design teams to ensure semiconductor quality.

Location: Catania, Italy

Salary: €31,200–€43,000 annually

Company

A global leader in semiconductor solutions, specializing in secure connectivity for embedded systems and automotive electronics.

What you will do

• Develop and implement verification environments and test benches using SystemVerilog and UVM.
• Create detailed verification plans based on design specifications and identify potential corner cases.
• Execute and debug test cases to thoroughly verify the design against specifications.
• Analyze simulation results and work closely with design engineers to resolve identified issues.
• Maintain verification collateral, including assertions, functional coverage models, and scripts.
• Collaborate with architecture and software teams throughout the product development lifecycle.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 2+ years of experience in digital IC design verification.
• Strong proficiency in SystemVerilog and UVM (Universal Verification Methodology).
• Experience with industry-standard simulation tools such as Questa, VCS, or Xcelium.
• Knowledge of scripting languages such as Python, Perl, or Tcl.
• Fluency in English, both written and spoken, is required.

Culture & Benefits

• Competitive benefits package based on the National Collective Labour Agreement (Metalmeccanica Industria).
• Fair, consistent, and transparent remuneration practices.
• Opportunity to work with cutting-edge semiconductor designs in a professional environment.
• Possibility of additional compensation through annual incentive opportunities and equity.