Digital Backend Design Engineer (IC Design)

TL;DR

Digital Backend Design Engineer (IC Design): Implementing digital designs from RTL to GDSII with an accent on physical design, timing closure, power optimization, and verification. Focus on building full-chip and block-level implementation flows, solving advanced-node PPA and signal-integrity challenges, and preparing designs for tapeout and final signoff.

Location: On-site in Paris or Tel Aviv

Company

An early-stage AI and computer hardware company developing technologies at the intersection of artificial intelligence and semiconductors.

What you will do

• Execute full-chip and block-level physical design, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Develop and optimize digital backend implementation flows using advanced EDA methodologies.
• Drive timing closure, power optimization, and PPA improvements.
• Perform LVS, DRC, ERC, IR drop, and electromigration analysis.
• Collaborate with RTL, DFT, packaging, and front-end design teams to resolve logical and physical interface issues.
• Support tapeout preparation and final signoff activities.

Requirements

• Master’s or PhD degree in Electrical or Electronic Engineering, or a related field.
• 4+ years of experience in digital IC backend implementation.
• Proficiency with Cadence Innovus and Genus.
• Strong knowledge of place and route, static timing analysis, DRC/LVS verification, IR drop, and electromigration analysis.
• Experience with advanced technology nodes, preferably 22nm or below, and hierarchical or full-chip implementation.
• Experience with Tcl scripting for backend flow automation; proficient English required.

Nice to have

• Experience with advanced hierarchical or full-chip implementation flows.
• French language skills.

Culture & Benefits

• Competitive cash compensation based on location, experience, and internal compensation benchmarks.
• Stock options are included in the majority of full-time offers.
• Relocation bonus and moving-expense coverage for relocation within 20 minutes of the company location.
• Healthcare coverage, pension contributions, professional development support, 25 days of paid time off, and public holidays.
• Ownership of a key technical domain with opportunities for technical and career growth.
• Multicultural, engineering-led, and high-paced working environment with public transport reimbursement of 50%.

Hiring process

• Screening call followed by a technical meeting about previous projects and achievements.
• CEO interview, reference calls with former managers, and a role-specific take-home technical assessment.
• Final interview to discuss the technical assignment and answer remaining questions.