Senior Ethernet Performance Engineer (AI)

TL;DR

Senior Ethernet Performance Engineer (AI/HPC): Leading performance validation and characterization of next-generation Ethernet-based networking silicon products with an accent on RoCEv2, RDMA, and high-performance compute environments. Focus on benchmarking fabrics, root-causing performance anomalies, and optimizing system throughput and latency for AI and HPC workloads.

Location: Remote (Must be residing within the United States). Occasional travel to Wayne, PA is required.

Company

hirify.global delivers high-performance scale-out networking solutions for AI and HPC datacenters.

What you will do

• Build, configure, and benchmark Ethernet fabrics with RoCEv2 for head-to-head evaluations against other network architectures.
• Develop and execute performance test plans for internal labs and real-world data center deployment scenarios.
• Analyze key performance metrics including throughput, latency, congestion, and power efficiency.
• Collaborate with customers and field teams to debug and optimize performance issues in production environments.
• Create diagnostic tools and scripts to collect, analyze, and visualize performance data.
• Provide actionable feedback to silicon and system design teams to resolve performance anomalies.

Requirements

• 7+ years of experience in post-silicon validation, performance engineering, or silicon debug for networking/HPC products.
• Strong understanding of networking protocols (Ethernet, PCIe) and congestion control (PFC, ECN, DCQCN).
• Proficiency in Python and Shell scripting for automation.
• Experience with data center performance requirements and benchmarks.
• Strong cross-functional communication skills and comfort working directly with customers.
• Must be residing within the United States.

Nice to have

• Deep understanding of DPDK, RDMA, or similar high-performance I/O frameworks.
• Background in silicon performance modeling or firmware/hardware co-design.
• Experience running HPC (MPI) and AI (NCCL/RCCL) benchmarks.
• Expertise in investigating PFC deadlocks and tail latency using kernel tools and fabric telemetry.

Culture & Benefits

• Competitive compensation package including equity, cash, and performance incentives.
• Comprehensive health, dental, and vision insurance, plus disability and life insurance.
• 401(k) plan with company match.
• Flexible work environment with Open Time Off (OTO), sick time, and paid holidays.
• Opportunity to collaborate with influential names in the semiconductor industry.