HSIO Subsystem RTL Design Engineer (AI)

TL;DR

HSIO Subsystem RTL Design Engineer (AI/UCIe): Designing and implementing D2D interconnect subsystems for AI accelerators with an accent on transaction management, link-level reliability, and microarchitecture definition. Focus on carrying next-generation D2D subsystems from specification to working silicon and optimizing high-speed communication between dies.

Location: Onsite in Seongnam, South Korea

Company

hirify.global is the first company to productize a UCIe-based die-to-die (D2D) interconnect for AI accelerators, creating single chiplet systems from multiple NPU dies.

What you will do

• Design and implement D2D interconnect subsystems, focusing on transaction management, datapath, and link-level reliability (retry/replay, CRC, FEC).
• Define subsystem microarchitecture in collaboration with architects, filling gaps left by industry specifications.
• Develop designs based on open D2D standards (UCIe) and integrate vendor controller/PHY IP via standard interfaces (RDI/FDI).
• Collaborate with verification, SoC integration, firmware, and PSI teams to ensure system-level functionality.
• Participate in silicon bring-up and post-silicon debugging, utilizing RTL simulation for deep-dive issue resolution.

Requirements

• 6–8 years of experience in RTL design using SystemVerilog/Verilog (M.S. and Ph.D. count towards this total).
• Proven experience across the full design lifecycle: architecture definition, RTL implementation, tape-out, and silicon bring-up.
• Hands-on design experience with link or protocol layers of high-speed interfaces (e.g., PCIe, CXL, Ethernet, or proprietary D2D links).
• Proficiency in logic simulation tools such as VCS and Xcelium.
• Experience with industry-standard quality flows, including Lint, CDC, DFT, and Synthesis.

Nice to have

• Direct experience with UCIe or other die-to-die interconnect technologies.
• Working understanding of SerDes-based high-speed links, including PCS/PMA partitioning and link training.
• Experience building design-for-debug structures such as loopback modes and performance monitors.
• Expertise in transaction ordering and flow control within AMBA/NoC-based systems.
• Experience integrating third-party controller/PHY IP through RDI/FDI or PIPE interfaces.

Culture & Benefits

• Work on the cutting edge of AI hardware, moving from evolving industry specs to productized silicon.
• Clear growth path into other high-speed IO domains like Ethernet and optical interconnects.
• Collaborative environment that values data-driven debugging and honest ownership of mistakes.
• Opportunity to own the communication backbone of a next-generation chiplet system.

Hiring process

• Document screening and online interview.
• On-site interview and culture-fit discussion.
• Compensation negotiation and final offer.