RTL Engineer (AI Accelerator)

Location: Seongnam, South Korea; on-site interviews and on-site work at the hirify.global office.

Company

hirify.global develops AI accelerators and a UCIe-based die-to-die interconnect that connects multiple NPU dies into a chiplet system.

What you will do

• Design and implement the D2D interconnect subsystem, including transaction management, datapath, retry/replay, CRC, FEC, built-in test, debug, and monitoring structures.
• Develop a system-level view of the NPU SoC and define the interconnect microarchitecture with the architect.
• Design against UCIe, CHI, and CHI C2C specifications and integrate vendor controller/PHY IP through RDI, FDI, AXI, and the in-house NoC interface.
• Collaborate with verification, SoC integration, firmware, PSI, and vendor teams.
• Participate in D2D link bring-up and support post-silicon debugging down to RTL simulation.

Requirements

• At least 6 years of combined RTL design experience using SystemVerilog or Verilog; fewer years may be considered with clear depth in interconnect or link-layer RTL.
• End-to-end ownership of at least one non-trivial RTL block.
• Proficiency with a logic simulation tool such as VCS or Xcelium and the ability to root-cause complex RTL issues.
• Familiarity with industry-standard quality flows, including Lint, CDC, and Synthesis.
• Strong collaborative cross-functional communication and a data-driven approach to debugging.

Nice to have

• Experience taking a design through tape-out and post-silicon debug.
• Working knowledge of AMBA, AXI/ACE, CHI, or another packetized on-chip protocol, including transaction ordering, outstanding-transaction management, and credit-based flow control.
• Experience with clock-domain crossing, reset-domain crossing, and power or clock gating in multi-domain designs.
• DFT experience with scan insertion, compression, and DFT-aware RTL practices.
• Understanding of SerDes-based high-speed links, including PCS/PMA partitioning, equalization, clock/data recovery, link training, and digital logic interfacing with a SerDes PHY.

Culture & Benefits

• Work closely with the interconnect architect on D2D architecture from specification through productized silicon.
• Opportunity to expand into Ethernet, optical interconnect, and other high-speed I/O domains.
• Prior UCIe or D2D experience is not required; strong interconnect RTL experience can be developed further on the project.
• Hiring process includes document screening, online interview, on-site interview, culture-fit interview, offer discussion, and final acceptance.