Principal Design Engineer (RTL)

TL;DR

Principal Design Engineer (RTL/Hardware): Designing and developing IP models for system-level memory and hardware-based verification with an accent on RTL design, verification, and protocol implementation. Focus on optimizing SDRAM, NAND Flash, and UFS models, ensuring product quality through cross-verification and customer collaboration.

Location: Shanghai, China

Company

Global leader in electronic design automation (EDA) software.

What you will do

• Design, develop, and support IP models for system-level memory, including SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.
• Perform RTL design, verification, productization, and documentation of memory IP.
• Interface with internal and external customers to resolve diverse problems related to emulation, simulation, and verification.
• Update, maintain, and document existing system-level memory model products.
• Collaborate on cross-verification and cross-training within the memory IP team to ensure high product quality.

Requirements

• MSEE or equivalent degree with a minimum of 5 years of experience in designing complex protocols and/or hardware systems.
• Fluent RTL design knowledge using Verilog/SystemVerilog.
• Proven experience using RTL verification tools and flows.
• Excellent written and spoken English communication skills.
• Strong debugging skills and ability to manage workload effectively in an agile environment.
• Experience with team-wide collaboration tools and processes.

Nice to have

• Verification experience using hirify.global simulation and/or emulation products.
• Programming proficiency in scripting languages such as Perl, TCL, or C-shell.
• Experience in memory sub-system design and operation.