Mixed Signal Logic Design Engineer

TL;DR

Mixed Signal Logic Design Engineer: Developing RTL design, simulation, and architecture for high-speed IP blocks and subsystems with an accent on mixed-signal fundamentals, low-power design, and physical implementation. Focus on optimizing power, performance, and area (PPA) goals while ensuring design integrity and supporting SoC integration.

Location: Must be based in Folsom, San Jose, or Santa Clara, California (On-site presence required)

Salary: $122,440–$232,190 USD

Company

hirify.global is a global leader in semiconductor technology, driving data-centric solutions through scalable engineering, custom ASIC development, and foundry enablement.

What you will do

• Develop logic design, RTL coding, and simulation for mixed-signal and high-speed IP blocks.
• Participate in the definition of architecture and microarchitecture features for designed blocks.
• Apply analog behavior modeling and circuit simulation to optimize logic for power, performance, area, and timing.
• Review verification plans and resolve failing RTL tests to ensure design correctness.
• Support SoC customers to ensure high-quality integration of IP blocks.

Requirements

• Must be eligible to work in the US without hirify.global immigration sponsorship.
• Bachelor's with 4+ years, Master's with 3+ years, or PhD with 1+ years of experience in Computer Science, Computer Engineering, or Electrical Engineering.
• Proficiency in RTL design and coding using System Verilog and Verilog.
• Expertise in mixed-signal fundamentals, low-power design (UPF), and clock gating.
• Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
• Experience with hardware simulation tools (VCS/Verdi) and Front End design tools (Lint, CDC, RDC, Synthesis).

Nice to have

• DDR Design domain knowledge (DFI/DDR/LPDDR protocols).
• Experience with AI tools like VSCode GitHub CoPilot.
• Familiarity with Formal Property Verification and Git version control.
• Experience with pre-silicon and post-silicon validation.

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work on cutting-edge semiconductor technology within a data-driven engineering organization.