Physical Design Engineer

TL;DR

Physical Design Engineer (Semiconductor): Performing physical design implementation of custom IP and SoC designs from RTL to GDS with an accent on synthesis, floor planning, and timing closure. Focus on optimizing designs for power, performance, and area while developing robust methodologies for semiconductor manufacturing.

Location: Must be based in the US (Folsom, CA or Austin, TX) with a hybrid work model.

Salary: $105,650–$200,340 USD

Company

hirify.global is a global leader in semiconductor technology, driving innovation in computing and data-driven engineering solutions.

What you will do

• Execute physical design implementation from RTL to GDS for custom IP and SoC.
• Perform synthesis, floor planning, place and route, and clock tree synthesis.
• Conduct static timing analysis, power integrity analysis, and layout verification.
• Analyze and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation.

Requirements

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 3+ years of experience in physical design (or 2+ years with a Master's degree).
• Must be eligible to work in the United States.
• Proficiency in RTL-to-GDS implementation flows.
• Experience with EDA tools such as Synopsys, Cadence, or Mentor Graphics.
• Strong knowledge of low-power design techniques.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work with industry experts on cutting-edge semiconductor technology.