Senior/Staff Design Verification Engineer (ASIC)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
TL;DR
Senior/Staff Design Verification Engineer (ASIC/UVM): Ensuring functional correctness and performance of computer arithmetic IPs through comprehensive verification environments with an accent on coverage-driven verification. Focus on developing formal verification testbenches, implementing complex stimulus, and debugging RTL issues using industry-standard EDA tools.
Location: Singapore / Penang, MY
Company
is a world-leading technology company specializing in Bitcoin mining solutions, ASIC chip design, and AI cloud capabilities.
What you will do
- Develop and implement state-of-the-art verification methodologies using UVM, C/C++, co-simulation, and formal verification.
- Collaborate with design teams to define and refine verification test plans based on design specifications.
- Implement test cases, stimulus, and patterns to validate DUT functionality and explore corner cases.
- Execute simulations and debug RTL issues using waveform analysis and advanced debugging tools.
- Maintain regression test suites and monitor functional and code coverage metrics for verification closure.
- Contribute to automation scripts, reusable verification components, and Verification IP (VIP).
Requirements
- Bachelorβs or Masterβs degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Solid understanding of digital logic design and RTL development using Verilog.
- Proficiency with AMBA bus protocols (AXI, AHB, APB).
- Hands-on experience with SystemVerilog, UVM, and formal verification tools (VC Formal or JasperGold).
- Familiarity with Linux/Unix environments and scripting for automation (Python, Bash, Perl).
- English: Strong written and verbal communication skills required.
Nice to have
- Proven track record of contributing to production-grade and silicon-proven IPs.
- Experience using AI Agents to improve verification productivity.
- Familiarity with RISC-V processor architecture or CPU verification concepts.
- Experience with C/C++ programming for testbench development.
Culture & Benefits
- Inclusive environment with an open workspace and an exciting start-up spirit.
- Opportunity to network with industrial pioneers and impact the digital asset industry.
- High level of personal accountability, autonomy, and fast growth opportunities.
- Attractive welfare benefits, including professional training and mentoring.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β