R&D Engineer (IC Design)

TL;DR

R&D Engineer (IC Design): Developing state-of-the-art IC solutions using CMOS cell-based ASIC technologies with an accent on the full development cycle from RTL analysis to post-prototype test support. Focus on full chip synthesis, STA, and physical design implementation for advanced process nodes like 16nm/7nm.

Location: Onsite in Shanghai, China (Zhangjiang Hi Tech)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Develop IC solutions utilizing leading-edge CMOS cell-based ASIC technologies.
• Manage key development phases including RTL analysis, synthesis, design optimization, and timing verification.
• Execute full chip synthesis and STA (DC, DCT, DCG) for 16nm/7nm design tape outs.
• Perform physical design implementation, including floor planning, placement, design closure, and DRC & LVS.
• Handle simulation, test insertion, vector generation, and post-prototype test support.

Requirements

• Solid VLSI background and deep understanding of ASIC design flow.
• Ability to handle block implementation and top-level tasks independently.
• Tapeout experience in 28nm or smaller process designs.
• Strong communication and problem-solving skills.
• Must be located in or able to work in Shanghai, China.

Nice to have

• Experience with DFT insertion.
• Knowledge of Power/IVD analysis.
• Proficiency in Perl or Tcl.

Culture & Benefits

• Opportunity to work on the latest 28nm/16FF designs.
• Collaborative team environment focused on personal career growth.
• Commitment to equal opportunity employment regardless of background.