R&D Physical Design Engineer (ASIC)

TL;DR

R&D Physical Design Engineer (ASIC): Implementing physical design for ASIC chips with an accent on floor planning, placement, and design closure. Focus on managing block implementation, executing full chip signoff tasks, and achieving tapeout success in 7nm and below processes.

Location: China-Shanghai-Zhangjiang Hi Tech (Onsite)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Perform physical design implementation, including floor planning, placement, and design closure.
• Handle block implementation and top-level tasks independently.
• Execute full chip signoff tasks, including PI, SI, PV, and STA.
• Ensure DRC and LVS compliance for high-performance designs.
• Collaborate on tapeout processes for advanced process nodes.

Requirements

• Solid VLSI background and deep understanding of ASIC design flow.
• Proven experience with tapeouts in 7nm or smaller process nodes.
• Bachelor's degree (8+ years exp) or Master's degree (7+ years exp) in Microelectronics or a related discipline.
• Strong problem-solving and communication skills.

Nice to have

• Experience with DFT insertion.
• Knowledge of Power/IVD analysis.
• Proficiency in Perl or Tcl scripting.