ASIC Physical Design Engineer

TL;DR

ASIC Physical Design Engineer (VLSI): Developing state-of-the-art IC solutions using leading-edge CMOS cell-based ASIC technologies with an accent on RTL analysis, synthesis, and physical design implementation. Focus on full chip synthesis, STA, and design closure for 16nm/7nm processes.

Location: Onsite in Shanghai, China (Zhangjiang Hi Tech)

Company

hirify.global is a global leader in semiconductor solutions, providing cutting-edge IC technologies for a wide range of applications.

What you will do

• Execute ASIC designs through key phases including RTL analysis, synthesis, and design optimization.
• Perform full chip synthesis and Static Timing Analysis (STA) for 16nm/7nm design tape outs.
• Implement physical design tasks such as floor planning, placement, and design closure.
• Conduct timing verification, simulation, test insertion, and vector generation.
• Provide post-prototype test support.

Requirements

• Solid VLSI background and deep understanding of the ASIC design flow.
• Proven experience with tapeouts in 28nm or smaller process designs.
• Ability to independently handle block implementation and top-level tasks.
• Strong communication and problem-solving skills.
• Master's degree in Microelectronics or a related discipline.

Nice to have

• Experience with DFT insertion.
• Knowledge of Power/IVD analysis.
• Proficiency in DRC/LVS.
• Scripting skills in Perl or Tcl.

Culture & Benefits

• Opportunity to work with leading-edge CMOS cell-based ASIC technologies.
• Collaborative team environment focused on career growth and professional development.
• Engagement with both internal and external customers to build state-of-the-art solutions.