Logic Design Engineer (SerDes)

TL;DR

Logic Design Engineer (SerDes): Designing and optimizing high-speed SerDes IP for next-generation products with an accent on RTL coding, microarchitecture definition, and simulation. Focus on meeting power, performance, area, and timing goals while ensuring high-quality integration into full chip designs.

Location: Hybrid in Santa Clara, California, US

Salary: $220,920 - $311,890 USD

Company

Global leader in semiconductor and AI technology, focusing on disruptive solutions for networks and edge computing.

What you will do

• Perform logic design of High Speed SerDes, including RTL coding and simulation for IP blocks and subsystems.
• Define architecture and microarchitecture features for the assigned blocks.
• Optimize logic to meet power, performance, area, and timing targets.
• Review verification plans and implement corrective measures for failing RTL tests.
• Support SoC customers to ensure high-quality integration and verification of IP blocks.
• Drive quality assurance compliance for IP SoC handoff.

Requirements

• Must be based in or eligible to work in the US (Santa Clara, CA).
• Bachelor's in Electrical/Computer Engineering (8+ years exp) or Master's (6+ years exp).
• 5+ years of experience in Mixed signal design, specifically High Speed SerDes architecture.
• Proficiency in System Verilog and detailed knowledge of SerDes PMA and PCS layers.
• Experience with OVM/UVM methodology and post-silicon validation.

Nice to have

• Experience collaborating with automated Place-and-route (APR) teams to close timing issues.
• Scripting skills in TCL, Perl, Python, or Ruby.

Culture & Benefits

• Competitive pay and stock bonuses.
• Comprehensive health, retirement, and vacation programs.
• Hybrid work model allowing split time between on-site and off-site.
• Opportunity to work on next-generation AI and network technology.