Principal Engineer, Design Verification (SoC)

TL;DR

Principal Engineer, Design Verification (SoC): Developing and maintaining UVM testbench components and verification collaterals for complex SoC architectures with an accent on design quality and test strategy. Focus on creating comprehensive test plans, debugging failures, and mentoring junior engineers to ensure high-performance compute and storage solutions.

Location: Westborough, MA

Salary: $178,200 - $263,740 per annum

Company

hirify.global provides semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Develop and maintain UVM testbench components and verification testing collaterals.
• Analyze architectures and designs to create comprehensive test plans and strategies.
• Lead the development of verification environments and methodologies.
• Develop tests and strategies to achieve specific coverage goals.
• Debug failures and collaborate with designers to resolve technical issues.
• Mentor junior engineers to expand their knowledge and technical skills.

Requirements

• Bachelor's degree in CS, EE, or related field with 10+ years of experience, or Master's/PhD with 7+ years.
• Strong experience with Verilog and SystemVerilog, specifically using UVM.
• Basic proficiency in C/C++.
• Experience with scripting languages such as Python or Perl.
• Working knowledge of the Linux operating system.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Employee stock purchase plan (ESPP) with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate milestones.
• Commitment to fair and authentic hiring practices.