Staff Design Verification Engineer (Semiconductor)

TL;DR

Staff Design Verification Engineer (UVM/SystemVerilog): Developing and maintaining UVM testbench components for complex SoC architectures with an accent on test plan creation and coverage goals. Focus on debugging failures, optimizing verification environments, and ensuring design quality for high-performance compute and automotive applications.

Location: Santa Clara, CA

Salary: $113,920 - $170,600 per annum

Company

hirify.global is a leader in semiconductor solutions providing essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Analyze SoC architectures and designs to create comprehensive test plans and strategies.
• Develop and maintain UVM testbench components and other verification testing collaterals.
• Implement testing strategies to achieve specific coverage goals.
• Debug design failures and collaborate closely with designers to resolve issues.
• Ensure overall design quality within a variety of complex SoC architectures.

Requirements

• Bachelor's degree in Computer/Electrical Engineering with 3+ years of experience, or Master's/PhD with 2+ years of experience.
• Proficiency in SystemVerilog and UVM.
• Experience writing and executing detailed verification test plans.
• Experience with verification tools, bug tracking, and regression mechanisms.
• Basic proficiency in C/C++ and scripting languages such as Python or Perl.
• Must be eligible to access export-controlled information as defined under U.S. export control laws (EAR).

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Financial well-being initiatives and recognition/service awards.