Principal Engineer - Digital IC Design (Semiconductor)

TL;DR

Principal Engineer - Digital IC Design (Semiconductor): Leading the development of next-generation high-speed PAM/Coherent DSPs and PHY designs using cutting-edge CMOS technology with an accent on micro-architecture, RTL development, and timing closure. Focus on driving complex SoC design cycles, collaborating with cross-functional teams, and providing technical mentorship to junior engineers.

Location: Pavia, Italy (Onsite)

Salary: €64,500–€86,000 per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential infrastructure for data centers, cloud, AI, and 5G networks.

What you will do

• Define sub-system architecture, micro-architecture, and register specifications for complex SoCs.
• Develop efficient RTL using Verilog/SystemVerilog and manage synthesis and backend integration.
• Design, debug, and support ICs, IPs, and block-level DFT structures.
• Collaborate with architecture, verification, floorplanning, and physical design teams to ensure quality.
• Perform static timing analysis, formal equivalence, CDC analysis, and functional verification.
• Provide technical guidance and mentorship to junior team members.

Requirements

• MS or PhD degree in Electrical Engineering or related field.
• Minimum 10 years of professional experience in digital IC design.
• Fluent in RTL coding, DFT, and ASIC design flow stages.
• Experience with multi-clock designs, synthesis, and static timing closure.
• Eligibility to access U.S. export-controlled technology.
• Effective communication and presentation skills.

Nice to have

• Design experience in high-speed (>1 GHz) DSP products.
• Proficiency in scripting languages such as Python, Perl, or Tcl.

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Collaborative, transparent, and inclusive work environment.
• Opportunities to work on industry-leading infrastructure technology.
• Focus on professional growth and long-term innovation.