Principal ASIC Design Engineer (Hardware)

TL;DR

Principal ASIC Design Engineer (Hardware): Leading the end-to-end design strategy for critical technologies powering quantum computers with an accent on ASIC/SoC development and system integration. Focus on translating evolving requirements into production-ready designs and shaping the long-term silicon roadmap.

Location: Hybrid: Must be based in Boulder, CO or Austin, TX

Company

hirify.global builds quantum computers using arrays of optically trapped neutral atoms to achieve unprecedented computational breakthroughs.

What you will do

• Lead end-to-end ASIC design strategy from requirements definition through silicon bring-up.
• Develop FPGA designs to identify architectures for scaling performance and density.
• Establish internal design processes across architecture, RTL, verification, and tapeout.
• Perform hands-on RTL development, microarchitecture, and integration.
• Coordinate milestones and vendor interfaces to ensure successful fabrication.
• Collaborate with quantum physicists and engineers to deliver hardware solutions.

Requirements

• MS or PhD in Electrical Engineering or a related field.
• 10+ years of post-degree experience in ASIC/SoC environments.
• Experience with 2 or more complete ASIC design cycles.
• Proficiency in RTL (SystemVerilog preferred) and implementing large DSP blocks.
• Experience porting designs from FPGA prototypes to ASICs.
• Knowledge of Cadence, Synopsys, or Siemens EDA tools.

Nice to have

• Mixed signal design experience.