Physical Design Engineer (SoC)

TL;DR

Physical Design Engineer (SoC): Executing RTL-to-GDS implementation for custom IP and SoC designs with an accent on synthesis, place-and-route, and static timing analysis. Focus on optimizing power, frequency, and area for high-performance computing applications.

Location: Hybrid in Penang, Malaysia

Company

hirify.global's Central Engineering Group (CEG) is a data-driven organization building scalable engineering solutions for IP, Custom ASIC, and Foundry Enablement.

What you will do

• Execute complete RTL-to-GDS implementation, including synthesis, place-and-route, clock tree synthesis, and floor planning.
• Perform static timing analysis (STA), power, noise, and reliability assessments.
• Conduct verification and signoff, including formal equivalence and layout verification.
• Resolve design violations to optimize for power, frequency, and area.
• Develop physical design methodologies and automate workflows using EDA tools.
• Collaborate with architecture and logic designers for seamless integration.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience (with Bachelor's), 4+ years (Master's), or 2+ years (PhD) in structural/physical design.
• Proficiency in RTL-to-GDS tools and methodologies.
• Deep expertise in static timing analysis and timing signoff using tools like Primetime.
• Strong scripting skills in Python, TCL, Perl, or Shell.
• Experience in multiple tape-outs for deep sub-micron process nodes.

Nice to have

• Advanced experience in I/O and IP timing budget development.
• Familiarity with Verilog or VHDL for hardware description.
• Experience mentoring junior team members.

Culture & Benefits

• Hybrid work model allowing a split between on-site and off-site work.
• Collaborative, diverse team environment focused on technological breakthroughs.
• Opportunity to work on industry-leading product portfolios and transformative technologies.