D2D/UCIe Solution Engineer (UCIe)

TL;DR

D2D/UCIe Solution Engineer (UCIe): Development and management of D2D subsystem and UCIe IP firmware for high-performance SoCs with an accent on silicon bring-up and validation. Focus on optimizing firmware implementation, debugging link-level issues, and building reusable firmware infrastructure.

Location: Onsite in Seongnam, South Korea

Company

AI chip startup focusing on high-performance SoC development for AI acceleration.

What you will do

• Develop and optimize D2D IP firmware tailored for the hirify.global SoC environment.
• Implement SoC firmware and validation workflows by extracting functional insights from Python-based test programs.
• Perform D2D link bring-up and validation across pre-silicon (simulation, emulation) and post-silicon (EVB) stages.
• Analyze D2D specifications and IP documentation to drive correct firmware behavior and link training sequences.
• Collaborate with architects and designers to debug PHY initialization, link training, and error handling.
• Build and maintain a reusable firmware infrastructure for current and future SoC generations.

Requirements

• 2+ years of experience (with Master's degree) or 5+ years of experience in embedded systems, device drivers, or system software.
• Proficiency in C, C++, and Python programming with strong firmware-level debugging skills.
• Ability to study and understand hardware specifications including D2D/UCIe, SerDes/PHY, and high-speed I/O protocols.
• Strong communication skills for effective collaboration within cross-functional architecture and design teams.

Nice to have

• Experience with at least one full silicon tape-out cycle from pre-silicon to post-silicon.
• Familiarity with high-speed interconnect protocols such as UCIe or PCIe.
• Knowledge of analog/PHY concepts including equalization, link training, and eye diagram interpretation.
• Experience with RTOS or bare-metal firmware development on ARM Cortex-A/M or RISC-V platforms.
• Hands-on experience with hardware validation tools such as JTAG, logic analyzers, and oscilloscopes.

Hiring process

• Document screening followed by online and on-site interviews.
• Culture-fit interview.
• Compensation negotiation and final offer.