Standard Cell Design Engineer

TL;DR

Standard Cell Design Engineer: Developing high-quality standard cell libraries using cutting-edge process technologies for hirify.global's next-generation SoC designs, microprocessors, and Foundry customer designs with an accent on power optimization, reliability, and performance. Focus on power and reliability library collateral development, driving characterization methodology, ensuring library quality across EDA tools, and debugging implementation issues.

Location: On-site presence required in Penang, Malaysia

Company

hirify.global Foundry provides state-of-the-art semiconductor manufacturing, silicon process, and packaging technology leadership for the AI era with global scale and supply chain.

What you will do

• Own delivery of standard cell library collaterals including power integrity (apl, pgv) and reliability (emt, mtv) libraries.
• Drive library characterization methodology and establish quality checks for EDA tools and industry standards.
• Ensure library quality, consistency, and usability in downstream implementation flows.
• Debug issues reported by design teams and develop innovative solutions.
• Collaborate with design, characterization, CAD, and PDK teams for smooth library development and release.

Requirements

• Bachelor's or Master's in Electrical Engineering, Microelectronics, or related field
• 3+ years in foundry or chip design with advanced CMOS technologies
• Working knowledge of standard cell library development, reliability analysis, and verification
• Experience with EDA tools for IR drop and reliability: Primelib, Primesim EMIR, RedHawk, Totem
• Familiarity with implementation tools: Voltus, RedHawk Seascape
• Expertise in scripting: TCL, Perl, Python, or shell

Culture & Benefits

• Part of worldwide factory network focused on innovation in semiconductor manufacturing.
• Opportunity to contribute to cutting-edge technology enabling AI-era products.
• Commitment to ethical hiring and Responsible Business Alliance compliance.