Senior Analog Layout Engineer (Analog IC)

TL;DR

Senior Analog Layout Engineer (Analog IC): Leading chip and block level layout for high-performance analog and mixed-signal products with an accent on high-resolution ADCs and precision voltage references. Focus on driving floorplan activities, managing physical verification environments, and mentoring layout teams to ensure zero-defect reliability.

Location: Catania, Italy

Company

A world leader in secure connectivity solutions for embedded applications serving automotive, industrial, IoT, and communication infrastructure markets.

What you will do

• Drive and deliver floorplan activities at both IP and SoC levels.
• Layout critical building blocks including 24-bit ADCs, precision voltage references, and HV chopper-stabilized amplifiers.
• Manage top-level integration using the Mixed Signal on Top flow.
• Lead and schedule activities for the SoC layout team and mentor junior engineers.
• Execute physical verifications including DRC, LVS, DFM, and parasitic extractions.
• Identify root causes and solutions for issues found in first prototypes.

Requirements

• 10+ years of experience leading Analog layout activities in complex ICs.
• Expertise in Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre).
• Strong knowledge of device physics and IC ESD protection strategies.
• Fluent English proficiency.
• Proven ability to manage and drive multisite layout teams in a global environment.

Culture & Benefits

• Access to online and offline learning opportunities for professional skill development.
• Commitment to sustainability with measurable year-on-year progress.
• Inclusive work environment with a strict policy against discrimination and harassment.
• Focus on diversity, inclusion, and equality within the workplace.