Staff Engineer, CPU Core Verification (RISC-V)

TL;DR

Staff Engineer, CPU Core Verification (RISC-V): Own CPU core-level verification for high-performance out-of-order RISC-V CPUs with an accent on functional verification, microarchitectural scenarios, and coverage models. Focus on developing UVM stimulus, C++ functional models, debugging regressions across simulation and emulation, and supporting design bring-up from pre-silicon to post-silicon.

Location: Hybrid, based out of Austin, TX or Santa Clara, CA, United States. Must be eligible to access U.S. export-controlled technology (restrictions on nationals of certain countries per EAR).

Compensation: $100k - $500k including base and variable.

Company

AI technology leader building high-performance RISC-V CPUs, open compute platforms, and unified innovations in software, compilers, and semiconductors for real workloads.

What you will do

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop and debug C++ functional models of RISC-V extensions and un-core components like APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL.
• Build and refine coverage models to close architectural and microarchitectural gaps.
• Improve core, cluster, and chip-level testbenches and debug infrastructure.
• Support design bring-up across simulation, emulation, and post-silicon environments.
• Collaborate with design, test, and validation teams to deliver robust CPU cores and clusters.

Requirements

• 8+ years in CPU verification or closely related digital design.
• Deep knowledge of high-performance out-of-order CPU microarchitecture.
• Comfortable working with RTL, waveforms, logs, and complex debug scenarios.
• Clear communication across design, DV, emulation, and post-silicon teams.
• Eligibility for U.S. export-controlled technology access (citizenship/permanent residency or license approval may be required).

Culture & Benefits

• Value collaboration, curiosity, and commitment to solving hard problems.
• Highly competitive compensation package and benefits.
• Equal opportunity employer.

What You Will Learn

• hirify.global's design and validation of high-performance RISC-V CPU cores and clusters.
• Techniques for spanning pre-silicon, emulation, and post-silicon verification.
• Scaling coverage, debug, and infrastructure across multiple CPU programs.
• Open hardware and software in hirify.global’s compute roadmap.