Назад
Company hidden
20 часов назад

Staff SoC Verification Engineer (AI)

Формат работы
remote (только Europe)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK/Netherlands
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Staff SoC Verification Engineer (SystemVerilog/UVM): Developing and maintaining verification environments for neuromorphic AI processors with an accent on functional coverage, constrained-random stimulus, and SoC-level validation. Focus on root-cause analysis of RTL bugs, automating verification flows, and mentoring junior engineers to ensure high-quality chip releases.

Location: Fully remote within the UK or Netherlands, or hybrid in the Netherlands (office 3 days per week).

Company

Semiconductor company developing ultra-efficient neuromorphic processors for edge AI to enable complex sensor analytics.

What you will do

  • Develop and maintain SystemVerilog/UVM verification environments at both module and SoC levels.
  • Define functional coverage models, write test sequences, and ensure coverage closure.
  • Debug simulation results using waveform tools and collaborate with design teams to resolve issues.
  • Drive constrained-random stimulus generation and continuous improvements in verification methodology.
  • Automate verification flows using modern EDA tools to maximize speed and quality.
  • Lead and mentor a small team while contributing to quality assurance and release-readiness.

Requirements

  • 8+ years of digital verification experience, including 4+ years of constrained-random verification with UVM.
  • 2+ years of embedded C development for SoC verification.
  • Experience designing verification architecture from specifications and creating test plans.
  • Proficiency in scripting with Python and working in Linux/bash environments.
  • Strong expertise in root-cause analysis and debugging SystemVerilog RTL.
  • Proven ability to lead and mentor a small team.

Nice to have

  • Experience with SystemC, UPF, or formal verification techniques.
  • Hands-on experience with FPGA validation, bring-up, or full-chip emulation.
  • Familiarity with OpenOCD/GDB for software-driven verification.
  • Experience in SystemVerilog RTL design.

Culture & Benefits

  • Competitive salary and pension plan.
  • Flexible working environment with a work-from-home policy and flexible hours.
  • Generous holiday scheme.
  • Inclusive culture that values openness, curiosity, and personal growth.
  • Office perks for those in the Netherlands, including fresh fruit, snacks, and an on-site gym.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →