Lead Design Engineer

TL;DR

Lead Design Engineer (DDR/HBM Physical Design): Focus on high speed digital DDR and HBM IP physical implementation, developing scripts and tools to enhance PD design flow with an accent on FP, CTS, STA, and physical verification. Focus on completing project tasks, solving design issues, analyzing PPA optimization methodologies, and implementing optimal flows for advanced nodes like TSMC 3nm/5nm.

Location: Shanghai

Company

EDA company delivering high-performance products based on advanced semiconductor processes up to TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm.

What you will do

• Implement high speed digital DDR and HBM IP physical design, including floorplan, CTS, STA, physical verification, and power analysis.
• Develop scripts or tools to improve PD design flow efficiency.
• Work on product projects: complete tasks, resolve design issues, provide checks to prevent recurrence.
• Analyze and summarize PPA optimization results, implement best parameters and flows across projects.

Requirements

• MS in EE with at least 3 years relevant IC design experience.
• Strong physical design experience in digital implementation: Floorplan, CTS, STA, physical verification, power analysis.
• Solid background in circuits, electronics, physics; willingness to learn new technologies for cutting-edge nodes.
• Skilled in scripting: Perl, C shell, TCL, Makefile, Python.
• Familiar with EDA tools: Innovus, ICC, Calibre, Tempus, PrimeTime.

Culture & Benefits

• Work on challenging high-frequency products up to 6400MHz using industry-leading processes.
• Gain rich experience and advanced methodologies in a team tackling FP, CTS, STA challenges.
• Opportunity to make an impact on technology innovation.