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2 дня назад

Principal ASIC Design Engineer

145 800 - 194 400CAD
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal ASIC Design Engineer (Datacenter AI SoCs): Participate in micro-architecture definition, RTL implementation, and verification of high-performance subsystems for datacenter and AI chips with an accent on low-power techniques, interface protocols, and timing closure. Focus on designing complex custom blocks like NPUs and AI accelerators, collaborating across design centers, and supporting post-silicon bring-up.

Location: Toronto, Canada

Salary: 145,800 - 194,400 CAD per annum

Company

hirify.global’s semiconductor solutions are essential building blocks for data infrastructure in enterprise, cloud, AI, and carrier architectures.

What you will do

  • Define micro-architecture for subsystems or full chips and write specifications.
  • Implement low-power RTL designs using SystemVerilog.
  • Collaborate with verification team on test plans, coverage, simulation, and debug.
  • Work with physical design for functional block implementation and timing closure.
  • Interact with project leads, multiple design centers, post-silicon team, software team, and customers.

Requirements

  • Bachelor’s in Computer Science, Electrical Engineering or related with 10+ years experience, or Master’s with 5+ years.
  • Fluent in SystemVerilog RTL coding.
  • Familiar with modern SoC architectures and interfaces like AXI, HBM, LPDDR/DDR, Ethernet, PCIe, D2D.
  • Experience in micro-architecture of complex ASICs in areas like NPU, AI accelerators, embedded processors, DSP, graphics, or microprocessors.
  • RTL design, synthesis, static-timing closure, formal verification, gate-level simulations, block verification.
  • High-speed design implementation and timing closure.
  • Position may require eligibility for U.S. export-controlled technology access; non-U.S. citizens/permanent residents may need export license approval.

Nice to have

  • Hands-on experience across full chip-development process with front-end tools.
  • Memory interface design (HBM, LPDDR/DDR).
  • Scripting in Python, Perl, Tcl, UNIX shell.

Culture & Benefits

  • Competitive compensation and comprehensive benefits.
  • Collaborative, transparent, inclusive work environment.
  • Tools and resources for success, growth, and development.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills in real time.
  • No AI tools permitted during interviews; use results in disqualification.

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