Senior RTL Design Engineer (AI)

TL;DR

Senior RTL Design Engineer (AI): Implementing parameterized RTL designs for high-performance AI hardware with an accent on architectural efficiency and PPA optimization. Focus on designing RISC-V based AI IPs and optimizing for performance, power, and area within a full compute stack.

Location: Hybrid based in Austin, TX or Toronto, ON

Salary: $100k - $500k (including base and variable compensation targets)

Company

hirify.global is leading the industry on cutting-edge AI technology, unifying innovations in software models, compilers, platforms, networking, and semiconductors to build a high-performance RISC-V CPU platform.

What you will do

• Implement parameterized RTL designs based on detailed micro-architecture specifications.
• Conduct synthesis, timing, and power experiments to evaluate and refine design efficiency.
• Develop and enhance RTL design environments, tools, and supporting infrastructure.
• Collaborate with architects to improve performance, power, and area (PPA) across designs.
• Integrate RTL improvements into a full AI compute stack to maximize real-world performance.

Requirements

• Bachelor’s degree in EE, ECE, CE, CS, or a related field.
• Strong experience in RTL design focused on power- and area-efficient architectures.
• Solid understanding of microprocessor architecture and logic design timing/power tradeoffs.
• Proficiency in Python and C/C++ for design automation and low-level development.
• Eligibility to access U.S. export-controlled technology (contingent upon citizenship/residency or license approval).

Nice to have

• Master's or PhD degree in a relevant field.

Culture & Benefits

• Highly competitive compensation package and comprehensive benefits.
• Collaborative and curious environment focused on solving complex hardware problems.
• Opportunity to work on a cutting-edge AI platform and RISC-V CPU from scratch.