Staff Design for Test STA Engineer (AI)

TL;DR

Staff Design for Test STA Engineer (DFT/STA): Ensuring the testability, quality, and performance of next-generation AI processors with an accent on DFT architecture and Static Timing Analysis. Focus on defining DFT methodologies, owning top-level timing constraints, and collaborating with Physical Design teams to achieve first-pass silicon success.

Location: Hybrid; Must be based in Santa Clara, CA or Austin, TX

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms to redefine computing paradigms.

What you will do

• Define and implement the full DFT methodology for high-speed, multi-core AI processor designs.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC).
• Own the STA sign-off for DFT modes at both block and top-level, including various corners and operating conditions.
• Collaborate with RTL, Physical Design, and Product Engineering teams to drive timing convergence and resolve complex violations.
• Identify and implement improvements to existing DFT and STA flows to enhance robustness and efficiency.
• Participate in ATE targeted test patterns, validation, and silicon debug.

Requirements

• Deep knowledge of core DFT concepts: Scan Compression, Memory BIST, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive expertise in Static Timing Analysis (STA) and proficiency with tools like Synopsys PrimeTime or Cadence Tempus.
• Strong understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), and timing sign-off modes.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.
• Must be eligible to access U.S. export-controlled technology (EAR compliance) based on citizenship or residency status.

Culture & Benefits

• Highly competitive compensation package including base and variable targets.
• Opportunity to work on cutting-edge AI hardware and RISC-V CPU architectures.
• Collaborative environment that values curiosity and commitment to solving hard technical problems.
• Equal opportunity employer.