Memory Architect (AI)

TL;DR

Memory Architect (AI): Designing and optimizing memory chiplet architectures for next-generation AI and CPU applications with an accent on bandwidth, latency, and power efficiency. Focus on developing performance/power modeling infrastructure, exploring state-of-the-art memory technologies, and integrating complex chiplets into SoCs.

Location: Remote or hybrid, based out of North America or South Korea. Must be eligible to access U.S. export-controlled technology (EAR compliance).

Compensation: $100k - $500k (including base and variable targets)

Company

hirify.global is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency through innovative chiplet-based SoCs.

What you will do

• Define architecture and micro-architecture specifications for memory and I/O chiplets for AI and CPU applications.
• Evaluate next-generation memory technologies, analyzing trade-offs in bandwidth, latency, and power to develop a strategic roadmap.
• Build and own a detailed performance and power modeling infrastructure for data-driven architectural decisions.
• Collaborate with SoC design, verification, physical design, packaging, and systems engineering teams for seamless integration.
• Coordinate and communicate frequently with external partners and customers.

Requirements

• 10+ years of experience in memory system architecture, scheduling algorithms, and controller architecture design.
• Deep understanding of JEDEC standard DRAMs (GDDR, HBM, LPDDR, DDR) and their specifications.
• Hands-on experience building performance/power simulators or developing memory IPs in HDL.
• Eligibility to access U.S. export-controlled technology (EAR compliance) is mandatory.
• Strong communication skills and a proven track record of mentoring junior engineers.

Nice to have

• PhD with a focus on computer architecture or a strong research/publication background.
• Experience with 3D-stacking, advanced packaging, custom memory, DFI, or die-to-die interfaces.
• Deep understanding of memory reliability and security.

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative, curiosity-driven environment focused on solving hard technical problems.
• Opportunity to work with world-class experts in AI, CPU, fabric, and system design.
• Exposure to the full chip lifecycle, from architecture specifications to silicon fabrication and mass production.