Technical Lead, Design Verification (AI)

TL;DR

Technical Lead, Design Verification (AI): Defining verification strategies and developing robust UVM environments for complex SoCs, ensuring functional correctness and driving continuous improvement of verification infrastructure with an accent on achieving thorough functional and code coverage closure. Focus on leading testbench reviews, coordinating with software and emulation teams, and using AI tools to enhance verification efficiency.

Location: Santa Clara, CA

Salary: 158,600 - 237,600 USD per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Develop SystemVerilog/UVM verification environments for complex SoCs, from block-level IPs through full-chip integration.
• Create detailed verification plans for block, IP, and SoC-level projects, ensuring comprehensive functional and code coverage.
• Architect UVM testbenches including stimulus generators, scoreboards, coverage models, and constrained random sequences.
• Collaborate closely with design, architecture, and software teams to manage milestones and ensure timely deliverables.
• Drive continuous improvement of verification methodologies and processes across the team.
• Build and optimize verification infrastructure regression frameworks, coverage tooling, and automation to improve efficiency.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of relevant experience, or Master's degree with 10+ years of experience, or PhD with 8+ years of experience.
• Strong proficiency in SystemVerilog with deep expertise in UVM methodology, including constrained random verification, coverage-driven techniques, and UVM library development.
• Proven track record achieving thorough functional and code coverage closure on complex SoC or IP tapeouts.
• Solid scripting skills in Python for verification automation, infrastructure, and tooling.
• Experience with industry simulators such as Xcelium, Questa, or VCS.
• Excellent communication skills with the ability to collaborate effectively across design, architecture, and software teams.

Nice to have

• Experience with protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, or UART.
• Experience with ARM/processor subsystem verification, memory controllers, NoC, or cache designs.
• Working knowledge of C/C++ for reference modeling or firmware-driven verification.
• Familiarity with gate-level simulation and post-silicon validation debug.
• Experience mentoring junior verification engineers.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.

Hiring process

• Candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.