Senior/Staff DFT Engineer (AI)

TL;DR

Senior/Staff DFT Engineer (AI): Designing, implementing, and validating test solutions for complex multicore in-memory-compute SoCs with an accent on scan insertion, ATPG, and memory BIST flows. Focus on silicon bring-up, debug optimization, and building robust design-for-test methodologies within a global semiconductor team.

Location: Remote from Europe/UK, or hybrid in Belgium, Netherlands, Switzerland, Italy, or the UK. Relocation possible to Italy or the Netherlands.

Company

A fast-growing deep-tech startup building next-generation AI platforms with $370M in funding and a global team of over 220 employees.

What you will do

• Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
• Collaborate with RTL, verification, and physical design teams to integrate DFT solutions.
• Support silicon bring-up and debug to optimize test coverage and yield.
• Contribute to methodology improvements and share best practices across the team.

Requirements

• 5+ years of experience in DFT engineering for complex SoCs.
• Proficiency in SystemVerilog RTL, TCL, and Python.
• Strong knowledge of hierarchical scan, ATPG, Memory BIST, and gate-level verification.
• Experience with Siemens, Synopsys, or Cadence DFT tools.
• Ability to work within a multicore SoC development environment.

Culture & Benefits

• Attractive compensation package including a pension plan.
• Extensive employee insurances and equity/shares options.
• Open and creative culture emphasizing collaborative ownership.
• Flexible work environment with remote and hybrid options across Europe.