Principal Engineer - Silicon Logical Design (AI)

TL;DR

Principal Engineer - Silicon Logical Design (AI): Driving technical leadership and architectural strategy for next-generation AI accelerator SoCs with an accent on RTL quality, micro-architecture development, and multi-year project execution. Focus on solving complex performance/power/area trade-offs, leading cross-functional design initiatives from specification through tape-out, and setting technical standards for the organization.

Location: Remote (anywhere in Europe/UK) or hybrid/onsite in Belgium, Netherlands, Switzerland, Italy, or UK. Relocation to Italy or the Netherlands is supported.

Company

hirify.global is a fast-growing, deep-tech startup developing a next-generation AI platform to achieve industry-leading performance and efficiency.

What you will do

• Define system-level architectures for AI accelerator SoCs aligned with long-term strategy.
• Lead large-scale RTL implementation and micro-architecture development from specification to tape-out.
• Drive cross-functional collaboration across verification, physical design, software, and product teams.
• Set and enforce organization-wide standards for RTL quality, design reviews, and engineering processes.
• Mentor senior engineers and provide technical vision to scale engineering impact.
• Lead post-silicon bring-up, validation, and complex root-cause analysis.

Requirements

• Must be based in Europe or the UK.
• Extensive experience in digital and logical design for complex SoCs with multiple successful tape-outs.
• Deep expertise in RTL and micro-architecture development using SystemVerilog and Verilog.
• Proven track record of delivering organization-wide, multi-year technical initiatives.
• Ability to influence technical direction without direct management authority.
• Strong understanding of performance, power, and area trade-offs in advanced process nodes.

Nice to have

• Experience with AI/ML accelerators, GPUs, NPUs, or high-performance compute architectures.
• Familiarity with industry-standard interconnects like AXI and NoC.
• Knowledge of low-power design techniques for multi-clock or multi-voltage systems.
• History of contributing to industry standards, patents, or technical publications.

Culture & Benefits

• Competitive compensation package including pension plan and insurance.
• Opportunity for company shares/equity.
• International environment with a distributed team of 220+ employees.
• Flexible working model with support for remote work or office-based collaboration.
• Open and collaborative culture that emphasizes innovation and ownership.