Formal Verification Engineer (Hardware)

TL;DR

Formal Verification Engineer (Hardware): Applying formal verification methods to complex digital designs with an accent on methodology development, test plan creation, and failure resolution. Focus on utilizing System Verilog and property-based model-checking to ensure design robustness within a high-performance mixed-signal environment.

Location: Must be based within a commutable distance of Austin, TX, or willing to relocate prior to the internship start.

Company

A global leader in mixed-signal processing solutions for top consumer brands, known for an inclusive and award-winning engineering culture.

What you will do

• Support the formal verification team in following and improving established methodology practices.
• Develop comprehensive test plans and verification strategies for microarchitecture and hardware designs.
• Perform failure analysis, resolution, and maintain detailed coverage reporting.
• Implement functional and formal verification environments to ensure design quality.

Requirements

• Currently enrolled in a MS or PhD program in Electrical or Computer Engineering.
• Must be able to access technical data without export license sponsorship.
• Proficiency in System Verilog and knowledge of SVA.
• Experience or knowledge in UVM or equivalent verification methodologies.
• Familiarity with scripting languages including Python, Perl, TCL, or Bash.
• Knowledge of property-based model-checking and digital design fundamentals.

Culture & Benefits

• Collaborative engineering-first work environment.
• Exposure to industry-leading mixed-signal processing challenges.
• Focus on inclusion, fairness, and professional growth.
• Regular in-office presence required (2-5 days per week depending on team needs).