Soc Clock, Reset And Peripheral Architecture Engineer

TL;DR

Soc Clock, Reset And Peripheral Architecture Engineer (SoC/AI Hardware): Leading the definition and architectural design of clock, reset, and peripheral subsystems for complex chiplet-based SoC systems with an accent on multi-chip package integration and power-domain management. Focus on ensuring architectural consistency across silicon, package, and board boundaries to enable robust, scalable silicon platforms.

Location: Seongnam, South Korea (Onsite)

Company

hirify.global is an AI semiconductor company specializing in high-performance hardware for scalable, reusable silicon platforms.

What you will do

• Define clock and reset architecture at the system and SoC levels across multi-chip and chiplet packages.
• Architect peripheral and GPIO subsystems to support diverse system use cases and configurations.
• Ensure architectural consistency across the SoC, package, and board boundaries.
• Collaborate with power architects to align designs with power states and DVFS strategies.
• Provide architectural guidance to design, physical, and firmware engineering teams throughout the exploration phase.

Requirements

• Master’s or higher degree in Electrical Engineering, Computer Science, or a related field.
• 5+ years of experience in SoC and system architecture.
• Comprehensive understanding of SoC design and clocking/reset design principles.
• Knowledge of power, clock, and reset domain interactions.
• Experience in peripheral and GPIO subsystem design.

Hiring process

• Document screening followed by an online interview.
• On-site interview and Culture-fit interview.
• Final compensation negotiation and offer.