Soc Pre-Silicon Verification Engineering Manager

TL;DR

Soc Pre-Silicon Verification Engineering Manager: Directing a team of design verification engineers responsible for SOC design verification, including building complex test-benches and testing environments from scratch with an accent on understanding hirify.global verification methodologies, verification environments and collateral creation. Focus on enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, and driving team results by inspiring people.

Location: Must have unrestricted, permanent right to work in Mexico

Company

hirify.global delivers exceptional products and delights customers with broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems.

What you will do

• Deploy and manage leading silicon design verification processes, procedures, verification tools, and technologies based on best industry practices.
• Work with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture.
• Collaborate with program leaders on the verification delivery and regression metrics against milestone requirements.
• Enable teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
• Shape future server SOC products by contributing to the architecture used across design families.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with at least 10 years additional experience or a Master's degree in the same fields with at least 8 years additional experience.
• 3 years of leadership experience in SoC or IP for SoC design or pre-silicon validation.
• Advanced English level.
• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Nice to have

• 5 years of Engineering Management experience.
• Experience in Verilog, SystemVerilog, JasperGold, OVM/UVM or Object Oriented Programming.
• Experience in all aspects of pre-silicon functional verification, including planning, debug, testbench design, UPF and coverage closure.

Culture & Benefits

• Encourages innovation, learning, team collaboration and thinking outside of the box to address all product development and customer-specific challenges.
• Committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
• Do not charge any fees during our hiring process.