RTL Design Engineer (AI)

TL;DR

RTL Design Engineer (AI): Leading the digital design and verification of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes with an accent on Verilog/SystemVerilog RTL, timing analysis, and design optimization. Focus on ensuring design quality, collaborating with cross-functional teams, and maintaining detailed documentation.

Location: Chandler, AZ or Irvine, CA, USA

Salary: $127,100 - $203,400

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Define digital architecture and verification strategies for complex AMS and IO subsystems.
• Design, synthesize, and verify Verilog/SystemVerilog RTL.
• Analyze and resolve Lint and CDC issues in the design.
• Optimize RTL for timing closure.
• Conduct formal verification of design.
• Generate timing constraints for Synthesis and STA.

Requirements

• MS +10 years of relevant industry experience.
• Experience with digital implementation flow from RTL synthesis to timing closure.
• Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
• Experience with Tessent tool for DFT insertion and verification.
• Proficient with Perl, Python, and Tcl scripting.
• Strong problem-solving skills with attention to detail.

Nice to have

• Solid understanding of transistor-level circuit behavior.
• Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
• Experience with advanced FinFET process nodes, including features, technology limitations, and PPA tradeoffs.

Culture & Benefits

• Medical, dental, and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays, paid sick leave and vacation time.