Principal Engineer, Physical Design Verification (Medtech)

TL;DR

Principal Engineer, Physical Design Verification (Medtech): Building and optimizing physical verification signoff processes for digital SoCs/ASICs with an accent on DRC/LVS/DFM closure, methodology definition, and tapeout release. Focus on driving signoff end-to-end, debugging connectivity issues, and ensuring system manufacturability and reliability.

Location: This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or Burlington, MA. For this role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship for employment visa status.

Salary: $200,000 (Burlington, MA) – $240,000 (SF Bay Area)

Company

hirify.global is a health-tech company leading a digital revolution in medical imaging with proprietary Ultrasound-on-Chip™ technology.

What you will do

• Drive end-to-end physical verification (PV) signoff for digital SoCs/ASICs, including methodology definition and tapeout release.
• Perform DRC/LVS/DFM closure, including hierarchical LVS debugging, connectivity issue resolution, and waiver governance.
• Understand how physical implementation choices (P&R/CTS/routing/ECOs) impact PV outcomes, schedule, and manufacturability.
• Develop scripting and automation using Python/Tcl/shell for reproducible flows, regression scaling, and metrics.
• Collaborate cross-functionally with PD/STA/power/IP owners to drive closure and make pragmatic signoff tradeoffs.
• Support block-to-top signoff integration and ensure third-party IP meets tapeout-quality acceptance criteria.

Requirements

• BS/MS/PhD in EE/CE or equivalent practical tapeout experience.
• 8–12+ years in physical verification (PV) signoff for digital SoCs/ASICs with multiple successful tapeouts.
• Strong hands-on expertise in DRC/LVS/DFM closure, including hierarchical LVS debugging and waiver governance.
• Proficiency with major PV tool stacks (e.g., Calibre-class flows) and strong understanding of PDK/rule deck intent.
• Solid understanding of how physical implementation choices impact PV outcomes and manufacturability.
• Strong scripting/automation skills (Python/Tcl/shell) for reproducible flows and regression scaling.

Nice to have

• Advanced node experience (28nm or smaller) and associated DFM complexity.
• Experience in regulated / high-reliability products where traceability and signoff rigor are critical.
• Familiarity with reliability/power integrity signoff concepts (EM/IR fundamentals).
• Experience interfacing with foundry/PDK vendors on rule updates and signoff collateral alignment.

Culture & Benefits

• Hybrid work model with team members spending two or more days a week in the office.
• Comprehensive health insurance (dental and vision), with annual contributions to Health Savings Account (HSA).
• 401k plan with company match.
• Opportunity to participate in Employee Stock Purchase Plan (ESPP).
• Unlimited Paid Time Off + 10 Holiday Days, and parental leave.
• Competitive salaried compensation and equity ownership.
• Comprehensive Employee Assistance Program for emotional health and day-to-day needs.