ASIC DFT Engineer (Semiconductor)

TL;DR

ASIC DFT Engineer (Semiconductor): Developing and implementing Design for Test (DFx) solutions for digital and mixed-signal IPs with an accent on testability, debug, and optimizing test costs. Focus on driving state-of-the-art DFx solutions and supporting chip teams for IP integration and silicon bring-up.

Location: USA-California-San Jose

Salary: $120,000 - $192,000 annually

Company

hirify.global is a global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

• Own IP DFT architecture, implementation, verification, and STA constraints for DFT.
• Optimize DFT architecture for test cost, test power, and physical design constraints.
• Deliver optimal retargetable ATPG patterns for usage across business units.
• Collaborate with front-end and back-end engineers to implement optimal DFx solutions.
• Support chip teams on IP DFT integration, pattern verification, and ATE bring-up.
• Participate in silicon bring-up, characterization, and yield recovery.

Requirements

• Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, boundary scan) covering digital logic, embedded memories, and Serdes PHY/IO’s.
• Experience in Scan architectural trade-off, coverage analysis, ATPG pattern generation, and verification.
• Experience in implementation of MBIST for memories and knowledge of repair schemes and algorithms.
• Well versed in JTAG standards (1149.1, 1149.6, 1687) and boundary scan.
• Strong Pre/Post Silicon debugging, analytical, and independent problem-solving ability.
• Strong knowledge of digital design, logical equivalence checking, and Gate level simulations with industry simulator tools.
• Experience in developing STA constraints for DFT logic/modes and working knowledge of Primetime.
• Post silicon experience on pattern bring-up, debug, and silicon characterization.
• Working knowledge of TCL, Perl, and shell scripting.
• Bachelors in Electrical or Computer Science Engineering with a minimum of 8+ years or a Master’s Degree with a minimum of 6+ years of relevant industry experience.

Nice to have

• Hands-on experience with Mentor/Siemens DFT Tessent tool suite for DFT insertion.
• Working knowledge of SERDES, Analog/mixed-signal DFT solutions (like IOBIST, AC boundary scan).

Culture & Benefits

• Competitive and comprehensive benefits package: Medical, dental, and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company-paid holidays, paid sick leave, and vacation time.
• hirify.global is an equal opportunity employer.