IP Logic Design Engineer

TL;DR

IP Logic Design Engineer: Defines and implements microarchitecture for cutting-edge IP blocks and subsystems for server processors, with an accent on RTL development and ensuring design quality. Focus on high-speed I/O protocols, coherency management, and supporting SoC integration and post-silicon activities.

Location: Hybrid (US, California, Santa Clara or US, Texas, Austin)

Salary: $122,440.00-200,340.00 USD annually

Company

hirify.global develops cutting-edge IPs that serve as foundational components for the next generation of server processors, specializing in the design and development of complex IP blocks and subsystems with a strong emphasis on IO architecture.

What you will do

• Define, document, and design the microarchitecture of IP blocks and subsystems.
• Own Register Transfer Level (RTL) development and implement logic components for IP blocks.
• Ensure design quality through clean partitioning, microarchitectural documentation, and review of RTL design.
• Apply strategies and tools to write RTL and optimize logic to meet power, performance, area, and timing goals.
• Deliver Microarchitecture Specifications (MAS) with detailed block diagrams, signal descriptions, and power/timing requirements.
• Review verification plans, debug failing RTL tests, and support SoC customers for high-quality integration.

Requirements

• Bachelor's or Master's Degree in Electrical, Electronics, or Computer Engineering.
• 5+ years of experience in IP design for SoC or ASIC products.
• Experience in chip design with familiarity of the entire development flow from definition to tape-out.
• Experience in high-speed I/O protocols (e.g., PCIe, CXL, Ethernet, proprietary interconnects).
• Proficiency in designing and verifying complex interface signals, including clock and power domain crossing.
• Hands-on experience with RTL design, simulation, debugging, triaging, running synthesis, and timing analysis.

Nice to have

• Experience with system simulation models and debugging RTL/tests.
• Experience in High-speed serial link protocols/IPs (PCIe, UPI, CXL, IOMMU etc).
• Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols.

Culture & Benefits

• Offers a total compensation package including competitive pay, stock bonuses, and benefit programs (health, retirement, vacation).
• Eligible for a hybrid work model allowing employees to split time between working on-site at assigned hirify.global sites and off-site.
• Committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.