TL;DR
Principal Digital IC Design Engineer (IoT): Architecting and implementing advanced SoC designs for compute, connectivity, and memory subsystems with an accent on micro-architecture, RTL development, and HW/SW co-design. Focus on ensuring functional correctness, timing closure, power optimization, and successful tapeout delivery.
Location: Onsite in Santa Clara, CA, USA. This position may require access to technology and/or software subject to U.S. export control laws and regulations, so applicants must be eligible to access export-controlled information as defined under applicable law. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Salary: $146,850 – $220,000 per annum
Company
hirify.global provides semiconductor solutions that are essential building blocks for data infrastructure across enterprise, cloud and AI, automotive, and carrier architectures.
What you will do
- Lead micro-architecture and RTL development for compute and connectivity subsystems.
- Drive HW/SW co-design and integration across multi-die SoC platforms.
- Collaborate with architects and DV engineers to ensure functional correctness, timing closure, and power optimization.
- Own RTL delivery milestones from ASR through PRQ, supporting emulation, silicon bring-up, and validation.
- Interface with external IP vendors and internal CAD teams to ensure IP integration and tool flow compatibility.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 10–15 years of experience, or Master’s/PhD with 5–10 years in digital IC design.
- Deep understanding of SoC architecture, processor subsystems, memory controllers, and high-speed interfaces.
- Expertise in Verilog/VHDL, RTL linting (Spyglass), CDC analysis, and synthesis readiness.
- Proficiency in scripting languages like Python and Perl for design automation.
- Proven success in delivering production-quality RTL under aggressive schedules.
- Experience with CXL, PCIe, DDR, and D2D protocols is highly desirable.
Culture & Benefits
- Total compensation package including base, bonus, and equity.
- Health and financial wellbeing benefits, including flexible time off and 401k.
- Year-end shutdown, floating holidays, and paid time off to volunteer.
- Commitment to fair and authentic hiring practices.
Hiring process
- Candidates are asked not to use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews; use of such tools will result in disqualification.
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