R&D Engineer IC Design (ASIC/Semiconductor)

TL;DR

R&D Engineer IC Design (ASIC/Semiconductor): Designing and debugging complex functional blocks for market-leading network switch products with an accent on micro-architecture, RTL coding, and synthesis. Focus on optimizing traffic manager and memory management units, resolving timing and congestion, and post-silicon bring-up and analysis.

Location: Onsite in San Jose, CA, USA. Must be legally authorized to work in the USA.

Salary: $120,000–$192,000 annually

Company

hirify.global is a global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

• Micro-architecture, design, RTL coding, debugging, and synthesis of complex functional blocks.
• Develop high-quality micro-architecture and design specifications.
• Conduct Verilog RTL coding and synthesis.
• Perform testplan reviews, assertions, debugging, and coverage analysis.
• Collaborate with Physical Design team on floor plans, timing, and congestion resolution.
• Execute post-silicon bring-up, debug, and failure analysis.

Requirements

• Bachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience.
• Experience in micro-architecture, design, RTL coding, and debugging.
• Proficiency in Verilog RTL coding and synthesis.
• Familiarity with testplan reviews, assertions, and coverage.
• Understanding of floor plan, timing, and congestion resolution.
• Experience with post-silicon bring-up and failure analysis.
• English B2+ required.

Culture & Benefits

• Competitive and comprehensive benefits package including Medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company-paid holidays, paid sick leave, and vacation time.
• Equal opportunity employer.