Senior ASIC Designer

Location: Stockholm; primarily onsite with a minimum of three days per week at the office. Candidates who can only work remotely may apply but will not be prioritized initially.

Company

hirify.global AB is a Sweden-based IT recruitment and consultancy company providing tailored technology solutions and recruiting services.

What you will do

• Own multiple ASIC/SoC projects from specification through tape-out and post-silicon bring-up.
• Define and document chip-level architectures, block diagrams, interface protocols, data and control flows, memory hierarchies, and DMA engines.
• Develop RTL and microarchitectures using Verilog/SystemVerilog, including clocking, resets, power domains, FSMs, pipelining, and parallelism.
• Collaborate with verification, physical design, firmware, and software teams on test plans, assertions, coverage, floorplanning, congestion, timing paths, and system integration.
• Perform PPA trade-off analysis, performance modeling, system-level simulations, and architectural evaluations.
• Lead cross-functional teams, review designs, mentor junior engineers, and communicate specifications with stakeholders.

Requirements

• 8–15+ years of experience in ASIC/SoC design and development.
• Expert-level proficiency in Verilog/SystemVerilog for RTL design.
• Experience developing microarchitecture specifications for complex subsystems.
• Familiarity with clocking, resets, power domains, FSMs, pipelining, and parallelism.
• Good understanding of functional verification methodologies, including SystemVerilog and UVM, and the ability to collaborate on test plans, assertions, and coverage.
• Familiarity with VCS, Questa, or ModelSim.
• Hands-on experience with Synopsys Design Compiler or Cadence Genus, SDC timing constraints, and PrimeTime timing closure.
• Ability to guide physical design teams on floorplanning, congestion, and timing paths.
• Experience defining interfaces such as AXI, PCIe, or Ethernet; memory hierarchies; DMA engines; and PPA trade-offs.
• Experience creating architectural specifications, ICDs, and design guides; knowledge of UPF/CPF, clock gating, power domains, and DVFS.
• Familiarity with DFT techniques including scan chains, MBIST, and boundary scan.
• Experience with performance modeling using Python, C/C++, or SystemC, plus system-level simulation and architectural evaluation.
• Proficiency in Python, Perl, or Tcl for design and flow automation.
• Strong debugging, problem-solving, verbal communication, written communication, and cross-functional leadership skills.

Nice to have

• Familiarity with High-Level Synthesis flows.
• Knowledge of AI/ML accelerators, networking, or video processing pipelines.
• Experience with multi-die chiplet integration and 2.5D/3D packaging.
• Understanding of security architectures, encryption modules, or hardware IP protection.
• Background in post-silicon validation, lab bring-up, or FPGA prototyping.
• Exposure to embedded firmware/software, drivers, or hardware-software co-design.

Culture & Benefits

• Work primarily from the Stockholm office in accordance with the client’s office policy.
• Remote-only candidates may apply, but onsite candidates are prioritized initially.
• Project engagement runs from 06.02.2026 through 31.12.2026.

Hiring process

• Applications must be submitted by 02.02.2026.
• hirify.global usually responds within one week.