Engineer, CPU Performance Verification (RISC-V)

Location: Hybrid, based out of Austin, Texas, or Santa Clara, California, United States

Compensation: $100k–$500k, including base and variable compensation targets; actual offers depend on experience, skills, education, background, and location.

Company

Tenstorrent develops AI technology and high-performance computing platforms spanning software models, compilers, platforms, networking, semiconductors, and RISC-V CPUs.

What you will do

• Drive CPU performance verification and correlation between RTL and the performance model.
• Collaborate with core architects and RTL engineers to meet performance goals, debug miscorrelation, and verify performance features.
• Draft performance test plans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
• Enhance tools and methodologies for performance analysis and correlation.
• Run performance experiments and evaluate techniques for optimizing power, performance, and area.

Requirements

• Experience analyzing modern CPU performance data, identifying bottlenecks, and building efficient analysis tools.
• Strong C++ and Python skills, with an understanding of industry-standard compilation, simulation, and emulation tools.
• Knowledge of the architecture and microarchitecture of high-performance CPU cores.
• Proficiency debugging RTL and logic across multiple design hierarchies and pre-silicon environments.
• Exposure to performance modeling and RTL-to-model correlation.
• Ability to identify problems and develop solutions.
• Must be eligible to access U.S. export-controlled technology; employment may depend on citizenship or permanent-residency status or prior license approval under U.S. export laws.

Culture & Benefits

• Highly technical, collaborative environment focused on solving difficult CPU design challenges.
• Competitive compensation package and benefits.
• Equal opportunity employer.
• Exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on optimization of CPU designs in pre-silicon and post-silicon phases.