Lead Design Engineer (ASIC Physical Design)

Location: Gyeonggi-do (Seoul), Republic of Korea

Company

hirify.global develops technology solutions and supports leaders and innovators working on advanced electronic design.

What you will do

• Implement physical design projects, including floor planning, power grid design, place and route, clock tree synthesis, and timing closure.
• Perform power and signal integrity signoff, physical verification including DRC, LVS, and antenna checks, EM/IR signoff, and DFM closure.
• Work on challenging low-power and high-speed designs at the latest technology nodes.
• Participate in or lead next-generation physical design methodology and flow development.
• Collaborate closely with the RTL design team to support successful tapeouts.

Requirements

• 9+ years of experience with ASIC design flow, hierarchical physical design strategies, methodologies, and deep sub-micron technology issues.
• Solid knowledge of low-power design, DFT, static timing analysis and closure, data skew balancing, and duty-cycle adjustment.
• Experience with EM/IR drop and crosstalk analysis, formal verification, physical verification, DFM, and P&R.
• Ability to take responsibility for varied technical tasks and work independently.
• Hands-on ability across design levels, including verifying, testing, and characterizing own designs.
• Self-motivated team player with good English communication skills.

Culture & Benefits

• Full-time position in hirify.global Korea.
• Opportunity to work on a variety of challenging designs and advanced technology nodes.
• Leadership opportunities in physical design methodology and flow development.