Senior Engineer, FPGA, MEO 1

Location: Betzdorf, Luxembourg; at least 60% onsite from the office. Travel is required for project realization purpohirify.global.

Company

hirify.global develops and operates satellite communications systems, including the meoSphere MEO satellite program for secure connectivity and high-speed broadband.

What you will do

• Evaluate and select radiation-tolerant FPGA, SoC, and ASIC solutions for satellite wireless architectures.
• Implement satellite radio access network and modem platforms from system and hardware specifications through RTL design.
• Design and optimize FPGA-based DSP algorithms under strict area, power, performance, and latency constraints.
• Review, integrate, and validate third-party firmware and software within FPGA systems.
• Support prototype testing, laboratory validation, hardware bring-up, system integration, and in-orbit demonstrations.
• Develop verification test benches, automated end-to-end test pipelines, design documentation, and verification reports.

Requirements

• Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of FPGA, SoC, or ASIC-based electronic equipment design experience, preferably in the space sector.
• Hands-on experience implementing FPGA, RFSoC, ASIC, and/or processor-based designs.
• Strong knowledge of digital equipment development flows, high-speed DSP PCB design, interconnects, integration, and testing.
• Solid theoretical and practical DSP background, including high-speed DSP blocks across multiple power and clock domains.
• Experience designing, implementing, and testing DSP algorithms in RTL, with Xilinx RFSoC or Versal Gen1/Gen2 platforms and Vivado IDE.
• Experience with mixed-signal ICs, ADCs, DACs, modems, channelizers, beamformers, high-speed SerDes, JESD204C, PCIe, Ethernet, CAN, SPI, I²C, and RS-422/485.
• Experience with FPGA internal logic analyzers such as ILA, Chipscope, or SignalTap, plus Tcl and Python scripting.
• Eligibility for a SECRET-level security clearance under applicable national regulations and EU/ESA/NATO equivalents is required.
• Fluency in English and the ability to manage multiple priorities and solve complex technical problems.

Nice to have

• UVM verification methodology.
• Experience with laboratory instruments such as logic analyzers and oscilloscopes.
• C or MATLAB programming.
• Fault-tolerant and space-reliability design, including SEU mitigation and system monitoring.
• High-speed interface design involving SerDes, Ethernet, or PCIe.
• Additional language skills.

Culture & Benefits

• Permanent employment.
• At least 60% onsite work from the Betzdorf office is required.
• Travel is required for project realization purpohirify.global.
• Work within a growing aerospace engineering program and a new manufacturing and test facility.
• Equal employment opportunity environment.